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RTL8201BL Datasheet(PDF) 14 Page - List of Unclassifed Manufacturers |
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RTL8201BL Datasheet(HTML) 14 Page - List of Unclassifed Manufacturers |
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14 / 29 page  RTL8201BL 2002-03-29 Rev.1.2 14 7. Functional Description The RTL8201BL Phyceiver is a physical layer device that integrates 10Base-T and 100Base-TX functions and some extra power manage features into a 48 pin single chip which is used in 10/100 Fast Ethernet applications. This device supports the following functions: MII interface with MDC/MDIO SMI management interface to communicate with MAC IEEE 802.3u clause 28 Auto-Negotiation ability Flow control ability support to cooperate with MAC Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO. Flexible LED configuration. 7-wire SNI(Serial Network Interface) support, works only on 10Mbps mode. Power Down mode support 4B/5B transform Scrambling/De-scrambling NRZ to NRZI, NRZI to MLT3 Manchester Encode and Decode for 10 BaseT operation Clock and Data recovery Adaptive Equalization Far End Fault Indication (FEFI) in fiber mode 7.1 MII and Management Interface 7.1.1 Data Transition To set the RTL8201BL for MII mode operation, pull MII/SNIB pin high and properly set the ANE, SPEED, and DUPLEX pins. The MII (Media Independent Interface) is an 18-signal interface which is described in IEEE 802.3u supplying a standard interface between PHY and MAC layer. This interface operates in two frequencies – 25Mhz and 2.5Mhz to support 100Mbps/10Mbps bandwidth for both the transmit and receive function. While transmitting packets, the MAC will first assert the TXEN signal and change byte data into 4 bits nibble and pass to the PHY by TXD[0..3]. PHY will sample TXD[0..] synchronously with TXC — the transmit clock signal supplied by PHY – during the interval TXEN is asserted. While receiving a packet, the PHY will assert the RXEN signal, pass the received nibble data RXD[0..3] clocked by RXC, which is recovered from the received data. CRS and COL signals are used for collision detection and handling. In 100Base-TX mode, when decoded signal in 5B is not IDLE, the CRS signal will assert and when 5B is recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble been confirmed and will be de-asserted when the IDLE pattern been confirmed. The RXDV signal will be asserted when decoded 5B are /J/K/and will be deasserted if the 5B are /T/R/or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal. The RXER (Receive Error) signal will be asserted if any 5B decode errors occur such as invalid J/K, T/R, invalid symbol, this pin will go high for one or more clock period to indicate to the reconciliation sublayer that an error was detected somewhere in the frame. The RTL8201BL does not use the TXER signal and will not affect the transmit function. 7.1.2 Serial Management The MAC layer device can use the MDC/MDIO management interface to control a maximum of 31 RTL8201BL devices, configured with different PHY addresses (00001b to 11111b). During a hardware reset, the logic levels of pins 9,10,12,13,15 are latched into the RTL8201BL to be set as the PHY address for serial management interface communication. Setting the PHY address to 00000b will put the RTL8201BL into power down mode. The read and write frame structure for the |
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