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RTL8201BL Datasheet(PDF) 15 Page - List of Unclassifed Manufacturers |
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RTL8201BL Datasheet(HTML) 15 Page - List of Unclassifed Manufacturers |
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15 / 29 page  RTL8201BL 2002-03-29 Rev.1.2 15 management interface follows. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 1 0 1 0 1 0 32 1s OP ST Preamble PHYAD[4:0] TA DATA REGAD[4:0] Idle MDC MDIO MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC Write Cycle D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 0 1 1 0 0 32 1s OP ST Preamble PHYAD[4:0] TA DATA REGAD[4:0] Idle MDC MDIO MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC Z MDIO is sourced by PHY. Clock data from PHY on rising edge of MDC Read Cycle Preamble 32 contiguous logic '1's sent by the MAC on MDIO along with 32 corresponding cycles on MDC. This provides synchronization for the PHY. ST Start of Frame. Indicated by a 01 pattern. OP Operation code. Read = 10. Write = 01. PHYAD PHY Address. Up to 31 PHYs can be connected to one MAC. This 5 bit field selects which PHY the frame is directed to. REGAD Register Address. This is a 5 bit field that selects which one of the 32 registers of the PHY this operation refers to. TA Turnaround. This is a two bit time spacing between the register address and the data field of a frame to avoid contention during a read transaction. For a read transaction, both the STA and the PHY shall remain in a high-impedance state for the first bit time of the turnaround. The PHY shall drive a zero bit during the second bit time of the turnaround of a read transaction. DATA Data. These are the 16 bits of Data. IDLE Idle Condition, not actually part of the management frame. This is a high impedance state. Electrically, the PHY's pull-up resistor will pull the MDIO line to a logic one. 7.2 Auto-negotiation and Parallel Detection The RTL8201BL supports IEEE 802.3u clause 28 Auto-negotiation operation which can cooperate with other transceivers supporting auto-negotiation. By this mechanism, the RTL8201BL can auto detect the link partner’s ability and determine the highest speed/duplex configuration and transmit/receive in this configuration. If the link partner does not support Auto-negotiation, then the RTL8201BL will enable half duplex mode and enter parallel detection. The RTL8201BL will default to transmit FLP and wait for the link partner to respond. If the RTL8201BL receives FPL, then the auto-negotiation process will go on. If it receives NLP, then the RTL8201BL will change to 10Mbps and half duplex mode. If it receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode. To enable the auto-negotiation mode operation on the RTL8201BL, just pull the ANE pin high. And the SPEED pin and DUPLEX pin will set the ability content of auto-negotiation register. The auto-negotiation mode can be externally disabled by pulling the ANE pin low. In this case, the SPEED pin and DUX pin will change the media configuration of the RTL8201BL. Below is a list for all configurations of the ANE/SPEED/DUPLEX pins and their operation in Fiber or UTP mode. Select Medium type and interface mode to MAC FX (pin 24) MII/SNIB (pin 44) Operation mode L H UTP mode and MII interface L L UTP mode and SNI interface H X Fiber mode and MII interface |
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