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COP8FGR540Q3 Datasheet(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # COP8FGR540Q3
Description  8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

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DC Electrical Characteristics (Continued)
−40˚C
≤ T
A ≤ +85˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Maximum Input Current without Latchup
(Note 7)
Room Temp.
±200
mA
RAM Retention Voltage, Vr
2.0
V
V
CC Rise Time from a VCC ≥ 2.0V
(Note 10)
12
µs
Input Capacitance
(Note 9)
7
pF
Load Capacitance on D2
(Note 9)
1000
pF
AC Electrical Characteristics
−40˚C
≤ T
A ≤ +85˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t
C)
Crystal/Resonator, External
4.5V
≤ V
CC ≤ 5.5V
0.67
µs
R/C Oscillator (Internal)
4.5V
≤ V
CC ≤ 5.5V
2
µs
Frequency Variation (Note 9)
4.5V
≤ V
CC ≤ 5.5V
±35
%
External CKI Clock Duty Cycle (Note 9)
fr = Max
45
55
%
Rise Time (Note 9)
fr = 10 MHz Ext Clock
12
ns
Fall Time (Note 9)
fr = 10 MHz Ext Clock
8
ns
Output Propagation Delay (Note 8)
R
L = 2.2k, CL = 100 pF
t
PD1,tPD0
SO, SK
4.5V
≤ V
CC ≤ 5.5V
0.7
µs
All Others
4.5V
≤ V
CC ≤ 5.5V
1.0
µs
MICROWIRE Setup Time (t
UWS) (Note
11)
20
ns
MICROWIRE Hold Time (t
UWH) (Note
11)
56
ns
MICROWIRE Output Propagation
Delay (t
UPD) (Note 11)
220
ns
Input Pulse Width (Note 9)
Interrupt Input High Time
1
t
C
Interrupt Input Low Time
1
t
C
Timer 1, 2, 3, Input High Time
1
t
C
Timer 1 2, 3, Input Low Time
1
t
C
Reset Pulse Width
1
µs
Note 3: tC = Instruction cycle time.
Note 4: Maximum rate of voltage change must be < 0.5 V/ms.
Note 5: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, External Oscillator, inputs connected to VCC and outputs driven low
but not connected to a load.
Note 6: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5 pro-
grammed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G Port data register.
Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
ESD transients.
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter characterized but not tested.
Note 10: Rise times faster than the minimum specification may trigger an internal power-on-reset.
Note 11: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See and the MICROWIRE
operation description.
www.national.com
8


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