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TPS70448 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS70448 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 32 page TPS70445, TPS70448, TPS70451, TPS70458, TPS70402 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RESET timing diagram VIN1 VUVLO VUVLO t t t MR Input RESET Output 120 ms Delay 120 ms Delay NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. VRES Output Undefined Output Undefined VRES PG1 timing diagram VPG t t t PG1 Output VIT+ (see Note B) VIN1 VOUT1 VPG1 VIT – (see Note B) VUVLO VUVLO PG1 NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. Threshold Voltage Output Undefined Output Undefined |
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