TPS70445, TPS70448, TPS70451, TPS70458, TPS70402

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003

4

POST OFFICE BOX 655303

detailed block diagram – adjustable voltage version

UVLO1

Thermal

Shutdown

Shutdown

2.5 V

+

–

Current

Sense

Reference

Vref

Vref

ENA_1

ENA_1

VIN1 (2 Pins)

GND

VIN2 (2 Pins)

VOUT1 (2 Pins)

FB1

(see Note A)

Falling Edge

Delay

VPGD_1

VSENSE1

Rising Edge

Deglitch

Current

Sense

+

–

ENA_2

ENA_2

Vref

PG1

MR

RESET

FB2

(see Note A)

VIN1

UVOL1

VPGD_2

VSENSE2

Rising Edge

Deglitch

PG2

UVOL2

UVLO1

VOUT2 (2 Pins)

EN1

EN2

VPGD1

VPGD2

2.5 V

UVLO2

ENA_1

ENA_2

Shutdown

UVLO2

NOTE A: For most applications, FB1 and FB2 should be connected to resistor dividers as close as possible to the device. For other

implementations, refer to FB terminals connection discussion in the application information section.