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TPS70458PWP Datasheet(PDF) 7 Page - Texas Instruments |
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TPS70458PWP Datasheet(HTML) 7 Page - Texas Instruments |
7 / 32 page TPS70445, TPS70448, TPS70451, TPS70458, TPS70402 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description The TPS704xx low dropout regulator family provides dual regulated output voltages with independent enable functions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good (PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete power solution. The TPS704xx, unlike many other LDOs, features very low quiescent current which remains virtually constant even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/β). The TPS704xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the full load range. pin functions enable (EN1 and EN2) The EN terminals are inputs which enable or shut down each respective regulator. If EN is at a logic high, the respective regulator will be in shutdown mode. When EN goes to voltage low, then the respective regulator is enabled. power good (PG1 and PG2) The PG terminals are open drain, active high outputs which indicate the status of each respective regulator. When the VOUT1 reaches 95% of its regulated voltage, PG1 will go to a high impedance state. When the VOUT2 reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance state when its respective output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage. The open drain outputs of the PG terminals require a pullup resistor. manual reset pin (MR) MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR (RESET) occurs. The terminal has a 6- µA pullup current to VIN1; however, it is recommended that the pin be pulled high to VIN1 when it is not used. sense (VSENSE1, VSENSE2) The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection should be as short as possible. Internally, the sense terminal connects to high-impedance wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way as to minimize/avoid noise pickup. Adding RC networks between sense terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to oscillate. FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize/avoid noise pickup. Adding RC networks between FB terminals and VOUTS to filter noise is not recommended because it can cause the regulators to oscillate. RESET indicator RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET goes into a high impedance state (i.e. logic high) after a 120 ms delay when both of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. If RESET is not used, it can be left floating. |
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