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TMS320C6713BGDP225 Datasheet(PDF) 94 Page - Texas Instruments |
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TMS320C6713BGDP225 Datasheet(HTML) 94 Page - Texas Instruments |
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94 / 150 page  TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS186I − DECEMBER 2001 − REVISED MAY 2004 94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table 46. C6713/13B Example Boards and Maximum EMIF Speed BOARD CONFIGURATION MAXIMUM ACHIEVABLE TYPE EMIF INTERFACE COMPONENTS BOARD TRACE SDRAM SPEED GRADE MAXIMUM ACHIEVABLE EMIF-SDRAM INTERFACE SPEED 143 MHz 32-bit SDRAM (−7) 100 MHz 1-Load One bank of one 1 to 3-inch traces with proper 166 MHz 32-bit SDRAM (−6) For short traces, SDRAM data output hold time on these 1-Load Short Traces One bank of one 32-Bit SDRAM pp termination resistors; Trace impedance ~ 50 Ω 183 MHz 32-bit SDRAM (−55) output hold time on these SDRAM speed grades cannot meet EMIF input hold time Trace impedance ~ 50 Ω 200 MHz 32-bit SDRAM (−5) meet EMIF input hold time requirement (see NOTE 1). 125 MHz 16-bit SDRAM (−8E) 100 MHz 2L d O bk f t 1.2 to 3 inches from EMIF to h l d i h 133 MHz 16-bit SDRAM (−75) 100 MHz 2-Loads Short Traces One bank of two 16-Bit SDRAMs each load, with proper termination resistors; 143 MHz 16-bit SDRAM (−7E) 100 MHz Short Traces 16-Bit SDRAMs termination resistors; Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6A) 100 MHz Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6) 100 MHz 125 MHz 16-bit SDRAM (−8E) For short traces, EMIF cannot meet SDRAM input hold requirement (see NOTE 1). 3L d One bank of two 1.2 to 3 inches from EMIF to h l d i h 133 MHz 16-bit SDRAM (−75) 100 MHz 3-Loads Short Traces One bank of two 32-Bit SDRAMs each load, with proper termination resistors; 143 MHz 16-bit SDRAM (−7E) 100 MHz Short Traces 32 Bit SDRAMs One bank of buffer termination resistors; Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6A) 100 MHz Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6) For short traces, EMIF cannot meet SDRAM input hold requirement (see NOTE 1). 143 MHz 32-bit SDRAM (−7) 83 MHz One bank of one 32 Bit SDRAM 166 MHz 32-bit SDRAM (−6) 83 MHz 3-Loads L T 32-Bit SDRAM One bank of one 4 to 7 inches from EMIF; T i d 63 Ω 183 MHz 32-bit SDRAM (−55) 83 MHz Long Traces One bank of one 32-Bit SBSRAM One bank of buffer Trace impedance ~ 63 Ω 200 MHz 32-bit SDRAM (−5) SDRAM data output hold time cannot meet EMIF input hold requirement (see NOTE 1). NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing requirements can be met for the particular system. |
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