NCP1203

http://onsemi.com

10

Power P1

Power P2

Power P3

Figure 17. Output Pulses at Various Power Levels (X = 5.0

ms/div) P1 t P2 t P3

Figure 18. The Skip Cycle Takes Place at Low Peak Currents which Guaranties Noise−Free Operation

315.40

882.70

1.450 M

2.017 M

2.585 M

300 M

200 M

100 M

0

MAX PEAK

CURRENT

SKIP CYCLE

CURRENT LIMIT

We recommend a pin 1 operation between 400 mV and

1.3 V that will fix the skip peak current level between

120 mV/Rsense and 390 mV/Rsense.

Non−Latching Shutdown

In some cases, it might be desirable to shut off the part

temporarily and authorize its restart once the default has

disappeared. This option can easily be accomplished

through a single NPN bipolar transistor wired between FB

and ground. By pulling FB below the Adj pin 1 level, the

output pulses are disabled as long as FB is pulled below

pin 1. As soon as FB is relaxed, the IC resumes its operation.

Figure 19 depicts the application example.