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AD1981BJST-REEL Datasheet(PDF) 4 Page - Analog Devices |
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AD1981BJST-REEL Datasheet(HTML) 4 Page - Analog Devices |
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4 / 28 page  REV. B –4– AD1981B Parameter Set Bits DVDD Typ AVDD Typ Unit POWER-DOWN STATES * (Fully Active) (No Bits Value) 42 51 mA ADC PR0 36 45 mA DAC PR1 29 35 mA ADC + DAC PR1, PR0 12 28 mA Mixer PR2 42 24 mA ADC + Mixer PR2, PR0 36 18 mA DAC + Mixer PR2, PR1 29 9 mA ADC + DAC + Mixer PR2, PR1, PR0 12 1.5 mA Standby PR5, PR4, PR3, PR2, PR1, PR0 0 0 mA Headphone Standby PR6 42 44 mA *Values presented with VREFOUT not loaded. Specifications subject to change without notice. Parameter Symbol Min Typ Max Unit RESET Active Low Pulsewidth tRST_LOW 1.0 ms RESET Inactive to BIT_CLK Start-Up Delay tRST2CLK 162.8 ns SYNC Active High Pulsewidth tSYNC_HIGH 1.3 ms SYNC Low Pulsewidth tSYNC_LOW 19.5 µs SYNC Inactive to BIT_CLK Start-Up Delay tSYNC2CLK 162.8 ns BIT_CLK Frequency 12.288 MHz BIT_CLK Frequency Accuracy ±1 ppm BIT_CLK Period tCLK_PERIOD 81.4 ns BIT_CLK Output Jitter 1, 2, 3 750 2000 ps BIT_CLK High Pulsewidth tCLK_HIGH 32.56 42 48.84 ns BIT_CLK Low Pulsewidth tCLK_LOW 32.56 38 ns SYNC Frequency 48.0 kHz SYNC Period tSYNC_PERIOD 20.8 ms Setup to Falling Edge of BIT_CLK tSETUP 5 2.5 ns Hold from Falling Edge of BIT_CLK tHOLD 5ns BIT_CLK Rise Time tRISECLK 246 ns BIT_CLK Fall Time tFALLCLK 246 ns SYNC Rise Time tRISESYNC 246 ns SYNC Fall Time tFALLSYNC 246 ns SDATA_IN Rise Time tRISEDIN 246 ns SDATA_IN Fall Time tFALLDIN 246 ns SDATA_OUT Rise Time tRISEDOUT 246 ns SDATA_OUT Fall Time tFALLDOUT 246 ns End of Slot 2 to BIT_CLK, SDATA_IN Low tS2_PDOWN 0 1.0 ms Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) tSETUP2RST 15 ns Rising Edge of RESET to Hi-Z Delay tOFF 25 ns Propagation Delay 15 ns RESET Rise Time 50 ns Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid 15 ns NOTES 1Guaranteed but not tested. 2Output jitter is directly dependent on crystal input jitter. 3Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower. Specifications subject to change without notice. Parameter Min Typ Max Unit CLOCK SPECIFICATIONS 1 Input Clock Frequency 24.576 MHz Recommended Clock Duty Cycle 40 50 60 % NOTES 1Guaranteed but not tested. 2Measurements reflect main ADC. Specifications subject to change without notice. TIMING PARAMETERS (Guaranteed over Operating Temperature Range) SPECIFICATIONS (continued) |
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