2003 Oct 13

9

Philips Semiconductors

Preliminary specification

High efficiency auto-up/down

DC/DC converter

TEA1211HN

7.12.2

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH

is defined as the STOP condition (P) (see Fig.7).

7.12.3

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period

of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.8).

7.12.4

The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited.

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by

the transmitter during which time the receiver generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master

receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave

transmitter (see Fig.9).

The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is

stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered).

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that

has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to

generate a STOP condition.

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SDA

SCL

P

STOP condition

SDA

SCL

S

START condition

MDB007

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MDB008

data line

stable;

data valid

change

of data

allowed

SDA

SCL