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IDT71V124SA20Y Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V124SA20Y Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 8 page 1 ©2000- Integrated Device Technology, Inc. AUGUST 2000 DSC-3873/05 Features x x x x x 128K x 8 advanced high-speed CMOS static RAM x x x x x JEDEC revolutionary pinout (center power/GND) for reduced noise x x x x x Equal access and cycle times – Commercial: 10/12/15/20ns – Industrial: 12/15/20ns x x x x x One Chip Select plus one Output Enable pin x x x x x Inputs and outputs are LVTTL-compatible x x x x x Single 3.3V supply x x x x x Low power consumption via chip deselect x x x x x Available in a 32-pin 300- and 400-mil Plastic SOJ, and 32-pin Type II TSOP packages. Functional Block Diagram Description The IDT71V124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno- vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh- speed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 5ns, with address access times as fast as 9ns available. All bidirec- tional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. ADDRESS DECODER 1,048,576-BIT MEMORY ARRAY I/O CONTROL • • • A0 A16 3873 drw 01 8 8 I/O0 -I/O7 8 • • • CONTROL LOGIC WE OE CS . 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout IDT71V124SA |
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