8705BY

www.icst.com/products/hiperclocks.html

REV. G JUNE 16, 2004

10

Integrated

Circuit

Systems, Inc.

ICS8705

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8705 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V

10

Ω

V

DDA

10

µF

.01

µF

3.3V

.01

µF

V

DD

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

and R2/R1 = 0.609.

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLK

nCLK

VDD