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GS72116AJ-8I Datasheet(PDF) 8 Page - GSI Technology |
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GS72116AJ-8I Datasheet(HTML) 8 Page - GSI Technology |
8 / 18 page Rev: 1.04a 10/2002 8/18 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS72116ATP/J/T/U Read Cycle 2: WE = VIH * These parameters are sampled and are not 100% tested. Write Cycle Parameter Symbol -7 -8 -10 -12 Unit Min Max Min Max Min Max Min Max Write cycle time tWC 7 — 8 — 10 — 12 — ns Address valid to end of write tAW 5 — 5.5 — 7 — 8 — ns Chip enable to end of write tCW 5 — 5.5 — 7 — 8 — ns Byte enable to end of write tBW 5 — 5.5 — 7 — 8 — ns Data set up time tDW 3.5 — 4 — 5 — 6 — ns Data hold time tDH 0 — 0 — 0 — 0 — ns Write pulse width tWP 5 — 5.5 — 7 — 8 — ns Address set up time tAS 0 — 0 — 0 — 0 — ns Write recovery time (WE)tWR 0 — 0 — 0 — 0 — ns Write recovery time (CE)tWR1 0 — 0 — 0 — 0 — ns Output Low Z from end of write tWLZ* 3— 3 — 3 — 3 — ns Write to output in High Z tWHZ* —3 — 3.5 — 4 — 5ns tAA tRC Address tAC tLZ tAB tBLZ tOE tOLZ CE UB, LB OE Data Out tHZ tBHZ tOHZ Data valid High impedance |
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