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66AK2H12AAAWA2 Datasheet(PDF) 9 Page - Texas Instruments |
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66AK2H12AAAWA2 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 354 page  66AK2H14/12/06 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SPRS866E—November 2012—Revised November 2013 10.5.5 Main PLL Controller/ARM/SRIO/HyperLink/PCIe/ USB Clock Input Electrical Data/Timing. . . . . . . 301 10.6 DDR3A PLL and DDR3B PLL . . . . . . . . . . . . . . . . . . . . . . . 304 10.6.1 DDR3A PLL and DDR3B PLL Control Registers 305 10.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.6.3 DDR3 PLL Input Clock Electrical Data/Timing 306 10.7 PASS PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 10.7.1 PASS PLL Local Clock Dividers . . . . . . . . . . . . . . . 307 10.7.2 PASS PLL Control Registers. . . . . . . . . . . . . . . . . . 307 10.7.3 PASS PLL Device-Specific Information . . . . . . . 309 10.7.4 PASS PLL Input Clock Electrical Data/Timing . 309 10.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 10.8.1 External Interrupts Electrical Data/Timing . . . 309 10.9 DDR3A and DDR3B Memory Controllers. . . . . . . . . . . 311 10.9.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 10.9.2 DDR3 Slew Rate Control . . . . . . . . . . . . . . . . . . . . 312 10.9.3 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 10.10 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 10.10.1 I2C Device-Specific Information . . . . . . . . . . . . 312 10.10.2 I2C Peripheral Register Description . . . . . . . . . 313 10.10.3 I2C Electrical Data/Timing. . . . . . . . . . . . . . . . . . 314 10.11 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 10.11.1 SPI Electrical Data/Timing. . . . . . . . . . . . . . . . . . 316 10.12 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 10.13 UART Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 10.14 PCIe Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 10.15 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 10.16 Security Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 10.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 10.18 SGMII/XFI Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 10.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem. .326 10.19.1 10GbE Supported Features . . . . . . . . . . . . . . . . .326 10.20 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 10.20.1 Timers Device-Specific Information . . . . . . . . .326 10.20.2 Timers Electrical Timing . . . . . . . . . . . . . . . . . . . .327 10.21 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . .327 10.21.1 Serial RapidIO Device-Specific Information . .327 10.22 General-Purpose Input/Output (GPIO) . . . . . . . . . . . .328 10.22.1 GPIO Device-Specific Information. . . . . . . . . . .328 10.22.2 GPIO Peripheral Register Description . . . . . . .328 10.22.3 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . .328 10.23 Semaphore2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 10.24 Universal Serial Bus 3.0 (USB 3.0) . . . . . . . . . . . . . . . . .329 10.25 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 10.25.1 EMIF16 Electrical Data/Timing . . . . . . . . . . . . . .330 10.26 Emulation Features and Capability . . . . . . . . . . . . . . .333 10.26.1 Chip Level Features . . . . . . . . . . . . . . . . . . . . . . . .334 10.26.2 ICEPick Module . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 10.27 Debug Port (EMUx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 10.27.1 Concurrent Use of Debug Port . . . . . . . . . . . . . .338 10.27.2 Master ID for HW and SW Messages. . . . . . . . .339 10.27.3 SoC Cross-Triggering Connection . . . . . . . . . . .340 10.27.4 Peripherals-Related Debug Requirement. . . .340 10.27.5 Advance Event Triggering (AET) . . . . . . . . . . . .342 10.27.6 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342 10.27.7 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . .343 A Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 B.1 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 B.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 |
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