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66AK2H12AXAAW2 Datasheet(PDF) 3 Page - Texas Instruments |
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66AK2H12AXAAW2 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 354 page Multicore DSP+ARM KeyStone II System-on-Chip (SoC) Copyright 2013 Texas Instruments Incorporated 66AK2H14/12/06 Features and Description 3 SPRS866E—November 2013 66AK2H14/12/06 Submit Documentation Feedback 1.5 Enhancements in KeyStone II The KeyStone II architecture provides many major enhancements over the previous KeyStone I generation of devices. The KeyStone II architecture integrates a Cortex-A15 processor quad-core cluster. The external memory bandwidth has been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with MSMC architecture improvements such as cache coherency. MSMC also enbles memories to operate at the speed of the processor cores, which reduces latency and contention while providing high-bandwidth interconnections between processor cores and shared internal and external memory. Multicore Navigator supports 2× the number of queues, descriptors, and packet DMA, 4× the number of micro RISC engines, and a significant increase in the number of push/pops per second compared to the previous generation. The new peripherals that have been added include the USB 3.0 controller, and asynchronous EMIF controller for NAND/NOR memory access. The 3-port Gigabit Ethernet switch in KeyStone I has been replaced with a 5-port Gigabit Ethernet switch in KeyStone II. Time synchronization support has been enhanced to reduce software workload and support additional standards like IEEE1588 Annex D/E and SyncE. The number of GPIOs and serial interface peripherals, like I 2C and SPI, have been increased to enable more board level control functionality. |
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