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66AK2H12BAAW24 Datasheet(PDF) 1 Page - Texas Instruments |
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66AK2H12BAAW24 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 354 page  Multicore DSP+ARM KeyStone II System-on-Chip (SoC) 66AK2H14/12/06 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Check for Evaluation Modules (EVM): EVMK2H SPRS866E—November 2012—Revised November 2013 1 66AK2H14/12/06 Features and Description 1.1 Features • Eight (66AK2H14/12) or Four (66AK2H06) TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Each With – Up to 1.2 GHz C66x Fixed/Floating-Point DSP Cores › 38.4 GMacs/Core for Fixed Point @ 1.2 GHz › 19.2 GFlops/Core for Floating Point @ 1.2 GHz –Memory › 32K Byte L1P Per CorePac › 32K Byte L1D Per CorePac › 1024K Byte Local L2 Per CorePac • ARM® Cortex™-A15 MPCore™ Processors Containing Four (66AK2H14/12) or Two (66AK2H06) ARM Cortex-A15 Cores – Up to 1.4-GHz Cortex-A15 Processor Core Speed – 4MB L2 Cache Memory Shared by All ARM CorePacs – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Instruction Cache and Data Cache per Cortex-A15 Processor Core – AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low Latency Access to Shared MSMC SRAM • Multicore Shared Memory Controller (MSMC) – 6 MB MSM SRAM Memory Shared by DSP CorePacs and ARM CorePac – Memory Protection Unit for Both MSM SRAM and DDR3_EMIF • Multicore Navigator – 16k Multi-Purpose Hardware Queues with Queue Manager – Packet-Based DMA for Zero-Overhead Transfers • Network Coprocessor – Packet Accelerator Enables Support for › Transport Plane IPsec, GTP-U, SCTP, PDCP › L2 User Plane PDCP (RoHC, Air Ciphering) › 1 Gbps Wire Speed Throughput at 1.5 MPackets Per Second – Security Accelerator Engine Enables Support for › IPSec, SRTP, 3GPP and WiMAX Air Interface, and SSL/TLS Security › ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5 › Up To 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering – Ethernet Subsystem › Five-Port Switch (four SGMII ports) •Peripherals – Four Lanes of SRIO 2.1 ›Supports Up To 5 GBaud › Supports Direct I/O, Message Passing – Two Lanes PCIe Gen2 ›Supports Up To 5 GBaud –TwoHyperLink › Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability ›Supports Up To 50 GBaud – 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 only) ›Two XFI Ports › IEEE1588 Support – Five Enhanced Direct Memory Access (EDMA) Modules – Two 72-Bit DDR3 Interfaces with Speeds Up To 1600 MHz –EMIF16 Interface –USB 3.0 –Two UART Interfaces –Three I 2C Interfaces –32 GPIO Pins – Three SPI Interfaces – Semaphore Module – 64-Bit Timers › Twenty 64-Bit Timers for 66AK2H14/12 › Fourteen 64-Bit Timers for 66AK206 – Five On-Chip PLLs • Commercial Case Temperature: – 0°C to 85°C • Extended Case Temperature: – - 40°C to 100°C |
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