Electronic Components Datasheet Search |
|
66AK2E05XABDA4 Datasheet(PDF) 9 Page - Texas Instruments |
|
|
66AK2E05XABDA4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 282 page 66AK2E05, 66AK2E02 www.ti.com SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015 3.1 C66x DSP CorePac The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8- bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. The C66x CPU also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000™ architecture (e.g., execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler. For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following documents: • TMS320C66x DSP CPU and Instruction Set Reference Guide (SPRUGH7) • TMS320C66x DSP Cache User's Guide (SPRUGY8) • TMS320C66x DSP CorePac User's Guide (SPRUGW0) 3.2 ARM CorePac The ARM CorePac of the 66AK2E0x integrates a Cortex-A15 Cluster (4 Cortex-A15 processors) with additional logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order, superscalar pipeline with integrated L1 caches. The implementation also supports advanced SIMDV2 (Neon technology) and VFPv4 (Vector Floating Point) architecture extensions, security, virtualization, LPAE (Large Physical Address Extension), and multiprocessing extensions. The quad core cluster includes a 4MB L2 cache and support for AMBA4 AXI and AXI Coherence Extension (ACE) protocols. For more information see the KeyStone II Architecture ARM CorePac User's Guide User Guide (SPRUHJ4). Copyright © 2012–2015, Texas Instruments Incorporated Device Characteristics 9 Submit Documentation Feedback Product Folder Links: 66AK2E05 66AK2E02 |
Similar Part No. - 66AK2E05XABDA4 |
|
Similar Description - 66AK2E05XABDA4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |