ADC12DS080 datasheet(10/34 Pages) TI1

Part #	ADC12DS080

Description	80 MSPS A/D Converter

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Manufacturer	TI1 [Texas Instruments]

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ADC12DS080

SNAS443A – MARCH 2008 – REVISED MARCH 2013

www.ti.com

Serial Control Interface Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50%

of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C

(1) (2)

Units

Parameter

Test Conditions

Typical(3)

Limits

(Limits)

fSCLK

Serial Clock Frequency

fSCLK = fCLK/10

8

MHz (max)

40

% (min)

tPH

SCLK Pulse Width - High

% of SCLK Period

60

% (max)

40

% (min)

tPL

SCLK Pulse Width - Low

% of SCLK Period

60

% (max)

tSU

SDI Setup Time

5

ns (min)

tH

SDI Hold Time

5

ns (min)

tODZ

SDO Driven-to-Tri-State Time

40

50

ns (max)

tOZD

SDO Tri-State-to-Driven Time

15

20

ns (max)

tOD

SDO Output Delay Time

15

20

ns (max)

tCSS

SCSb Setup Time

5

10

ns (min)

tCSH

SCSb Hold Time

5

10

ns (min)

Minimum time SCSb must be deasserted

Cycles of

tIAG

Inter-Access Gap

3

between accesses

SCLK

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described

in the Operating Ratings section. See Figure 2.

(2)

With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

LVDS Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50%

of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C

(1) (2)

Units

Parameter

Test Conditions

Typical(3)

Limits

(Limits)

LVDS DC CHARACTERISTICS

Output Differential Voltage

250

mV (min)

VOD

RL = 100Ω

350

(SDO+) - (SDO-)

450

mV (max)

delta

Output Differential Voltage Unbalance

RL = 100Ω

±25

mV (max)

VOD

1.125

V (min)

VOS

Offset Voltage

RL = 100Ω

1.25

1.375

V (max)

delta VOS Offset Voltage Unbalance

RL = 100Ω

±25

mV (max)

IOS

Output Short Circuit Current

DO = 0V, VIN = 1.1V,

-10

mA (max)

LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS

tDP

Output Data Bit Period

Dual-Lane Mode

2.08

ns

Output Data Edge to Output Clock Edge

tHO

Dual-Lane Mode

990

550

ps (min)

Hold Time(4)

Output Data Edge to Output Clock Edge

tSUO

Dual-Lane Mode

1100

600

ps (min)

Set-Up Time(4)

tFP

Frame Period

Dual-Lane Mode

25

ns

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described

in the Operating Ratings section. See Figure 2.

(2)

With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(4)

This parameter is ensured by design and/or characterization and is not tested in production.

10

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