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ADC121S101-Q1 Datasheet(PDF) 3 Page - Texas Instruments

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Part # ADC121S101-Q1
Description  Single-Channel, 0.5 to 1-Msps, 12-Bit Analog-to-Digital Converter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC121S101-Q1 Datasheet(HTML) 3 Page - Texas Instruments

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1
V
A
6
CS
2
GND
5
SDATA
3
V
IN
4
SCLK
1
V
A
6
CS
2
GND
5
SDATA
3
V
IN
4
SCLK
3
ADC121S101, ADC121S101-Q1
www.ti.com
SNAS304H – JANUARY 2006 – REVISED APRIL 2016
Product Folder Links: ADC121S101 ADC121S101-Q1
Submit Documentation Feedback
Copyright © 2006–2016, Texas Instruments Incorporated
(1)
All devices are fully pin and function compatible.
5 Device Comparison Table
(1)
RESOLUTION
SPECIFIED SAMPLE RATE RANGE
50 TO 200 KSPS
200 TO 500 KSPS
500 KSPS TO 1 MSPS
12 Bits
ADC121S021
ADC121S051
ADC121S101
10 Bits
ADC101S021
ADC101S051
ADC101S101
8 Bits
ADC081S021
ADC081S051
ADC081S101
6 Pin Configuration and Functions
NGF Package
6-Pin WSON
Top View
DBV Package
6-Pin SOT-23
Top View
(1)
G = Ground, I = Input, O = Output, P = Power
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
1
VA
P
Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to
GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor located within 1 cm of the power pin.
2
GND
G
The ground return for the supply and signals.
3
VIN
I
Analog input. This signal can range from 0 V to VA.
4
SCLK
I
Digital clock input. This clock directly controls the conversion and readout processes.
5
SDATA
O
Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.
6
CS
I
Chip select. On the falling edge of CS, a conversion process begins.
PAD
GND
G
For package suffix CISD(X) only. TI recommends connecting the center pad to ground.


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