ADS5203

SBAS258A – JUNE 2002 – REVISED JULY 2002

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7

TIMING DIAGRAMS

Analog_A

Analog_B

DA[9:0]

DB[9:0]

DAB[19:0]

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

A&B 1

A&B 2

A&B 3

A&B 4

A&B 5

t

0

1

2

3

4

5

6

7

8

9

1011

12

1314

151617

18

Sample A1 and B1

DAB[19:0] is used to illustrate the placement of the busses DA and DB

ADCOUTA[9:0](3)

ADCOUTB[9:0](3)

COUT

COUT

d(o)

CLK(1)

CLK40INT(2)

NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.

Figure 1. Dual Bus Output—Option 1.

Analog_A

Analog_B

DA[9:0]

DB[9:0]

DAB[19:0]

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

A&B 1

A&B 2

A&B 3

A&B 4

A&B 5

89

10

12

3

4

5

6

7

Sample A1 and B1

DAB[19:0] is used to illustrate the combined busses DA and DB

ADCOUTA[9:0](2)

ADCOUTB[9:0](2)

COUT

COUT

CLK(1)

NOTE: (1) In this option CLK = 40MHz, per channel. (2) Internal signal only

Figure 2. Dual Bus Output—Option 2.

Not Recommended For New Designs