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ADS5296ARGCT Datasheet(PDF) 10 Page - Texas Instruments |
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ADS5296ARGCT Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 107 page  Input Clock Frequency = fS LCLKP LCLKN Output Data Rate = 12x fS Input Signal Sample N tA CLKN CLKP D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 ADCLKN ADCLKP Bit Clock Frequency = 6x fS Frame Clock Frequency = 1x fS OUTP OUTN Sample N-1 Sample N Latency = 12 Clocks Sample N + 12 Sample N + 11 Sample N + 13 tPDI D1 D0 D3 D2 D11 D10 D9 D8 OUTP OUTN GND Logic 0 V = 350 mV - ODL (1) Logic 1 V = +350 mV ODH (1) V OCM ADS5296A SBAS631 – OCTOBER 2013 www.ti.com PARAMETRIC MEASUREMENT INFORMATION Figure 1 shows a timing diagram of the LVDS output voltage levels. (1) With an external 100- Ω termination. Figure 1. LVDS Output Voltage Levels Figure 2 shows the latency timing diagram. Figure 2. Latency Timing Diagram 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS5296A |
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