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ADS5411IPJYRG3 Datasheet(PDF) 5 Page - Texas Instruments |
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ADS5411IPJYRG3 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 25 page  ADS5411 SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010 www.ti.com 5 TIMING CHARACTERISTICS(3) Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS PARAMETER DESCRIPTION MIN TYP MAX UNIT Aperture Time tA Aperture delay 500 ps tJ Clock slope independent aperture uncertainty (jitter) 150 fs kJ Clock slope dependent jitter factor 50 µV Clock Input tCLK Clock period 9.5 ns tCLKH(1) Clock pulse width high 4.75 ns tCLKL(1) Clock pulse width low 4.75 ns Clock to DataReady (DRY) tDR Clock rising 50% to DRY falling 50% 2.8 3.9 4.7 ns tC_DR Clock rising 50% to DRY rising 50% tDR + tCLKH ns tC_DR_50% Clock rising 50% to DRY rising 50% with 50% duty cycle clock 7.6 8.7 9.5 ns Clock to DATA, OVR(4) tr Data VOL to data VOH (rise time) 2 ns tf Data VOH to data VOL (fall time) 2 ns L Latency 3 Cycles tsu(C) Valid DATA(2) to clock 50% with 50% duty cycle clock (setup time) 1.8 3.4 ns tH(C) Clock 50% to invalid DATA(2) (hold time) 2.6 3.6 ns DataReady (DRY) to DATA, OVR(4) tsu(DR)_50% Valid DATA(2) to DRY 50% with 50% duty cycle clock (setup time) 1.6 2.6 ns th(DR)_50% DRY 50% to invalid DATA(2) with 50% duty cycle clock (hold time) 3.9 4.4 ns (1) See Figure 1 for more information. (2) See VOH and VOL levels. (3) All values obtained from design and characterization. (4) Data is updated with clock rising edge or DRY falling edge. N N+1 N+2 N+3 N+4 N N−1 N−2 N−3 tA tsu(C) th(C) th(DR) N + 1 N N + 2 N + 3 N + 4 tC_DR tr tCLK tCLKL CLK, CLK D[13:0], OVR DRY AIN tCLKH tDR tsu(DR) tf Figure 1. Timing Diagram |
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