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ADS5423IPJYG3 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS5423IPJYG3 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 28 page  ADS5423 SLWS160A − FEBRUARY 2005 − REVIISED JANUARY 2010 www.ti.com 6 PIN CONFIGURATION 15 16 D3 D2 D1 D0 (LSB) DMID GND DRVDD OVR DNC AVDD GND AVDD GND 39 38 37 36 35 34 33 32 31 30 29 28 27 17 1 2 3 4 5 6 7 8 9 10 11 12 13 DRVDD GND VREF GND CLK CLK GND AVDD AVDD GND AIN AIN GND 18 19 20 21 PJY PACKAGE (TOP VIEW) 51 50 49 48 47 52 46 44 43 42 45 22 23 24 25 26 41 40 14 GND PIN ASSIGNMENTS TERMINAL NAME NO. DESCRIPTION DRVDD 1, 33, 43 3.3 V power supply, digital output stage only GND 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 Ground VREF 3 2.4 V reference. Bypass to ground with a 0.1- µF microwave chip capacitor. CLK 5 Clock input. Conversion initiated on rising edge. CLK 6 Complement of CLK, differential input AVDD 8, 9, 14, 16, 18, 22, 26, 28, 30 5 V analog power supply AIN 11 Analog input AIN 12 Complement of AIN, differential analog input C1 20 Internal voltage reference. Bypass to ground with a 0.1- µF chip capacitor. C2 24 Internal voltage reference. Bypass to ground with a 0.1- µF chip capacitor. DNC 31 Do not connect OVR 32 Overrange bit. A logic level high indicates the analog input exceeds full scale. DMID 35 Output data voltage midpoint. Approximately equal to (DVCC)/2 D0 (LSB) 36 Digital output bit (least significant bit); two’s complement D1−D5, D6−D12 37−41, 44−50 Digital output bits in two’s complement D13 (MSB) 51 Digital output bit (most significant bit); two’s complement DRY 52 Data ready output |
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