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ADS5440 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS5440 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 29 page www.ti.com TIMING CHARACTERISTICS N N+1 N+2 N+3 N+4 N N−1 N−2 N−3 tA tsu_c th_c th_DR N + 1 N N + 2 N + 3 N + 4 tC_DR tCLK tCLKL CLK, CLK D[12:0], OVR, OVR DRY, DRY AIN tCLKH tDR tsu_DR T0073-01 tr tf TIMING CHARACTERISTICS ADS5440 SLAS467A – JULY 2005 – REVISED DECEMBER 2005 Figure 1. Timing Diagram Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 210 MSPS, AV DD = 5 V, DRVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tA Aperature delay 500 ps tJ Clock slope independent aperture uncertainty (jitter) 150 fs RMS Latency 4 cycles Clock Input tCLK Clock period 4.76 ns tCLKH Clock pulsewidth high 2.38 ns tCLKL Clock pulsewidth low 2.38 ns Clock to DataReady (DRY) tDR Clock rising to DataReady falling 1.1 ns tC_DR Clock rising to DataReady rising Clock duty cycle = 50% (1) 3.1 3.5 3.9 ns Clock to DATA, OVR(2) tr Data rise time (20% to 80%) 0.6 ns tf Data fall time(80% to 20%) 0.6 ns tsu_c Data valid to clock (setup time) 3.5 ns th_c Clock to invalid Data (hold time) 0.2 ns DataReady (DRY)/DATA, OVR(2) tsu(DR) Data valid to DRY 2.1 2.4 ns th(DR) DRY to invalid Data 0.9 1.3 ns (1) tC_DR = tDR + tCLKH for clock duty cycles other than 50% (2) Data is updated with clock falling edge or DRY rising edge. 6 Submit Documentation Feedback |
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