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ADS5440-EP Datasheet(PDF) 9 Page - Texas Instruments

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Part # ADS5440-EP
Description  13-BIT 210-MSPS ANALOG-TO-DIGITAL CONVERTER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS5440-EP Datasheet(HTML) 9 Page - Texas Instruments

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DEFINITION OF SPECIFICATIONS
ADS5440-EP
SGLS359 – AUGUST 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
3, 8, 13, 14, 19, 21,
AVDD
23, 25, 27, 31, 35, 37, Analog power supply
39
DVDD
1, 51, 66
Output driver power supply
2, 7, 9, 12, 15, 18, 20,
GND
22, 24, 26, 28, 30, 32, Ground
34, 36, 38, 40, 52, 65
VREF
6
Reference voltage
CLK
10
Differential input clock (positive). Conversion initiated on rising edge.
CLK
11
Differential input clock (negative)
AIN
16
Differential input signal (positive)
AIN
17
Differential input signal (negative)
Over range indicator LVDS output. A logic high signals an analog input in excess of the
OVR, OVR
42, 41
full-scale range.
D0, D0
50, 49
LVDS digital output pair, least-significant bit (LSB)
D1–D6, D1–D6
53–64
LVDS digital output pairs
D7–D11, D7–D11
67–76
LVDS digital output pairs
D12, D12
78, 77
LVDS digital output pair, most-significant bit (MSB)
DRY, DRY
80, 79
Data ready LVDS output pair
NC
4, 5, 29, 33, 43–48
No connect
Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic
high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is
performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart.
The DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined by a least
squares curve fit of that transfer function. The INL at each analog input value is the difference between the
actual transfer function and this best fit line, measured in units of LSB.
Gain Error
The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the
nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters
over the whole temperature range divided by TMIN – TMAX.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding
the power at dc and the first five harmonics.
9
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