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ADC08B200 Datasheet(PDF) 4 Page - Texas Instruments |
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ADC08B200 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 39 page  VD GND VD GND VD GND 50k ADC08B200 SNAS388F – MARCH 2007 – REVISED APRIL 2013 www.ti.com Pin No. Symbol Equivalent Circuit Description Output Edge Select or Test Mode Enable input. If this input is high, the data outputs transition with the rising edge of the 14 OEDGE/TEN DRDY output. If this input is low, the data outputs transition with the falling edge of the DRDY output. Forcing a potential of VA/2 at this input enables the Test Mode. Synchronized WEN output. The WEN control input is 18 WENSYNC synchronized on-chip with the internal sample clock and is provided at this output. Data Ready output. This signal transitions with the transition of 31 DRDY the digital data outputs and indicates that the output data is ready. 26 thru 29 and D0–D7 Digital data digital Outputs. D0 is the LSB, D7 is the MSB. 33 thru 36 Buffer Full Flag. This output is high when the capture buffer is 16 FF full. Buffer Empty Flag. This output is high when the capture buffer 15 EF is empty. Auto-Stop Write input. This pin has a dual function. With the buffer enabled, this pin acts as the ASW input. When this input is high, writing to the buffer is halted when the capture 25 ASW buffer is full (FF high). When the buffer is disabled, this pin is ignored. When the device is in Test Mode, this pin acts as the Output Edge Select signal, functioning in accordance with the description of the OEDGE/TEN pin. Buffer Size input. These inputs determine the size of the 23,24 BSIZE(1:0) buffer, as described in the Functional Description. Clock Multiply Factor input. These inputs determine the 38, 39 MULT(1:0) internal clock PLL's multiplication factor. Positive analog supply pin. Connect to a voltage source of 1, 4, 12 VA +3.3V. 43, 44, 48 VP PLL supply pin. Connect to a voltage source of +3.3V. 40 VD Digital core supply pin. Connect to a voltage source of +3.3V. Power supply for the output drivers. Connect to a voltage 32 VDR source of 2.7V to VD. 2, 5, 8, 11, 21, GND The ground return for the chip core. 42, 45, 47 7 SIG GND Analog input signal ground. 30 DR GND The ground return for the output drivers. 4 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: ADC08B200 |
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