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ADC08B200-Q1 Datasheet(PDF) 11 Page - Texas Instruments

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Part # ADC08B200-Q1
Description  200 MSPS A/D Converter with Capture Buffer
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC08B200-Q1 Datasheet(HTML) 11 Page - Texas Instruments

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THD = 20 x log
+ . . . + A
A
f2
2
f10
2
Af1
2
ADC08B200
www.ti.com
SNAS388F – MARCH 2007 – REVISED APRIL 2013
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code
value. The end point test method is used. Measured at 200 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the
power in the second and third order intermodulation products to the power in one of the original
frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is defined as the
difference between the voltage required to cause the first code transition and the ideal voltage (1/2 LSB)
to cause that transition.
VOFF = VZT − 1/2 LSB = VZT - (VRT − VRB) / 512
where
VZT is the first code transition input voltage
(2)
OUTPUT DELAY is the time delay after the rising edge of the RCLK input before the data update is present at
the output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of CLK or RCLK output.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that
data is presented to the output driver stage. New data is available at every clock cycle, but the data lags
the conversion by the Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08B200, PSRR1 is the ratio of the change in Full-Scale Error that results from
a change in the DC power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c.
signal riding upon the power supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output
to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal at the output to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal at the output and the peak spurious signal, where a spurious signal is any signal present in
the output spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
where
Af1 is the RMS power of the fundamental (output) frequency
Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum
(3)
Copyright © 2007–2013, Texas Instruments Incorporated
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