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ADC08D500CIYB Datasheet(PDF) 11 Page - Texas Instruments |
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ADC08D500CIYB Datasheet(HTML) 11 Page - Texas Instruments |
11 / 48 page ADC08D500 www.ti.com SNAS274F – MAY 2005 – REVISED APRIL 2013 Converter Electrical Characteristics (continued) The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (1) (2) Typical Limits Units Symbol Parameter Conditions (3) (3) (Limits) CLOCK INPUT CHARACTERISTICS 0.4 VP-P (min) Sine Wave Clock 0.6 2.0 VP-P (max) VID Differential Clock Input Level 0.4 VP-P (min) Square Wave Clock 0.6 2.0 VP-P (max) II Input Current VIN = 0 or VIN = VA ±1 µA Differential 0.02 pF CIN Input Capacitance (7) (8) Each input to ground 1.5 pF DIGITAL CONTROL PIN CHARACTERISTICS VIH Logic High Input Voltage See (9) 0.85 x VA V (min) VIL Logic Low Input Voltage See (9) 0.15 x VA V (max) CIN Input Capacitance (8) (10) Each input to ground 1.2 pF DIGITAL OUTPUT CHARACTERISTICS 400 mVP-P (min) Measured differentially, OutV = VA, 710 VBG = Floating, (11) 920 mVP-P (max) VOD LVDS Differential Output Voltage 280 mVP-P (min) Measured differentially, OutV = GND, 510 VBG = Floating, (11) 720 mVP-P (max) Change in LVDS Output Swing Δ VO DIFF ±1 mV Between Logic Levels VOS Output Offset Voltage, see Figure 1 VBG = Floating 800 mV VOS Output Offset Voltage, see Figure 1 VBG = VA (11) 1200 mV Output Offset Voltage Change Δ VOS ±1 mV Between Logic Levels IOS Output Short Circuit Current Output+ & Output- connected to 0.8V −4 mA ZO Differential Output Impedance 100 Ohms VOH Cal_Run High level output IOH = -400uA (9) 1.65 1.5 V VOL Cal_Run Low level output IOH = 400uA (9) 0.15 0.3 V POWER SUPPLY CHARACTERISTICS PD = PDQ = Low 561 665 mA (max) IA Analog Supply Current PD = Low, PDQ = High 340 408 mA PD = PDQ = High 1.8 mA PD = PDQ = Low 200 275 mA (max) IDR Output Driver Supply Current PD = Low, PDQ = High 112 157 mA (max) PD = PDQ = High 0.012 mA PD = PDQ = Low 1.4 1.78 W (max) PD Power Consumption PD = Low, PDQ = High 0.8 1.0 W PD = PDQ = High 3.5 mW Change in Full Scale Error with change PSRR1 D.C. Power Supply Rejection Ratio 30 dB in VA from 1.8V to 2.0V PSRR2 A.C. Power Supply Rejection Ratio 248 MHz, 50mVP-P riding on VA 51 dB (7) The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. (8) This parameter is specified by design and is not tested in production. (9) This parameter is specified by design and/or characterization and is not tested in production. (10) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. (11) Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above. Tying VBG to the supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical). Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADC08D500 |
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