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ADS131A02IPBSR Datasheet(PDF) 11 Page - Texas Instruments |
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ADS131A02IPBSR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 85 page 11 ADS131A02, ADS131A04 www.ti.com SBAS590A – MARCH 2016 – REVISED MARCH 2016 Product Folder Links: ADS131A02 ADS131A04 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.8 Timing Requirements: Synchronous Master Interface Mode over operating free-air temperature range (unless otherwise noted) 1.65 V ≤ IOVDD ≤ 2.7 V 2.7 V < IOVDD ≤ 3.6 V UNIT MIN MAX MIN MAX tc(CLKIN) External clock period Single device 64 40 ns Multiple device chaining 88 56 tw(CP) Pulse duration, CLKIN high or low Single device 32 20 ns Multiple device chaining 44 28 tc(SC) SCLK period 2tCLKIN 2tCLKIN ns tw(SCHL) Pulse duration, SCLK high or low tCLKIN tCLKIN ns tsu(DI) Setup time, DIN valid before SCLK falling edge 5 5 ns th(DI) Hold time, DIN valid after SCLK falling edge 8 8 ns 7.9 Switching Characteristics: Synchronous Master Interface Mode over operating ambient temperature range (unless otherwise noted) 1.65 V ≤ IOVDD ≤ 2.7 V 2.7 V < IOVDD ≤ 3.6 V UNIT MIN MAX MIN MAX tp(SCDOD) Propagation delay time, first SCLK rising edge to DOUT driven 28 15 ns tp(SCDO) Propagation delay time, SCLK rising edge to valid new DOUT 26 15 ns tp(SDR) Propagation delay time, SCLK falling edge to DRDY falling edge 31 20 ns th(LSB) Hold time, last SCLK falling edge to DOUT 3-state HIZDLY = 00 6 30 6 20 ns HIZDLY = 01 8 37 8 27 HIZDLY = 10 10 43 10 43 HIZDLY = 11 12 47 12 47 tp(DRS) Delay time, last SCLK rising edge to DRDY rising edge 17 15 ns (1) Only valid if CLKSRC = 0 7.10 Timing Requirements: Synchronous Slave Interface Mode over operating free-air temperature range (unless otherwise noted) 1.65 V ≤ IOVDD ≤ 2.7 V 2.7 V < IOVDD ≤ 3.6 V UNIT MIN MAX MIN MAX tc(CLKIN) External clock period(1) Single device 64 40 ns Multiple device chaining 88 56 tw(CP) Pulse duration, CLKIN high or low(1) Single device 32 20 ns Multiple device chaining 44 28 td(SCS) Delay time, SCLK falling edge to CS falling edge 6 4 ns td(CSSC) Delay time, CS falling edge to first SCLK rising edge 16 16 ns tc(SC) SCLK period Single device 64 40 ns Multiple device chaining 88 64 tw(SCHL) Pulse duration, SCLK high or low Single device 32 20 ns Multiple device chaining 44 32 tsu(DI) Setup time, DIN valid before SCLK falling edge 5 5 ns th(DI) Hold time, DIN valid after SCLK falling edge 8 6 ns td(SCCS) Delay time, last SCLK falling edge to CS rising edge 5 5 ns |
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