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ADS1255IDBR Datasheet(PDF) 6 Page - Texas Instruments |
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ADS1255IDBR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 45 page  ADS1255 ADS1256 SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013 www.ti.com 6 PARAMETER MEASUREMENT INFORMATION SCLK CS DIN DOUT t1 t3 t2H t4 t5 t2L t6 t9 t8 t7 t11 t10 Figure 1. Serial Interface Timing TIMING CHARACTERISTICS FOR FIGURE 1 SYMBOL DESCRIPTION MIN MAX UNIT t SCLK period 4 τCLKIN(1) t1 SCLK period 10 τDATA(2) t SCLK pulse width: high 200 ns t2H SCLK pulse width: high 9 τDATA t2L SCLK pulse width: low 200 ns t3 CS low to first SCLK: setup time(3) 0 ns t4 Valid DIN to SCLK falling edge: setup time 50 ns t5 Valid DIN to SCLK falling edge: hold time 50 ns t6 Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC, RREG Commands 50 τCLKIN t7 SCLK rising edge to valid new DOUT: propagation delay(4) 50 ns t8 SCLK rising edge to DOUT invalid: hold time 0 ns t9 Last SCLK falling edge to DOUT high impedance NOTE: DOUT goes high impedance immediately when CS goes high 6 10 τCLKIN t10 CS low after final SCLK falling edge 8 τCLKIN RREG, WREG, RDATA 4 τCLKIN Final SCLK falling edge of command to first SCLK RDATAC, SYNC 24 τCLKIN t11 Final SCLK falling edge of command to first SCLK rising edge of next command. RDATAC, RESET, STANDBY, SELFOCAL, SYSOCAL, SELFGCAL, SYSGCAL, SELFCAL Wait for DRDY to go low (1) τCLKIN = master clock period = 1/fCLKIN. (2) τDATA = output data period 1/fDATA. (3) CS can be tied low. (4) DOUT load = 20pF ⎥⎥ 100kΩ to DGND. |
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