 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADS1278MPAPTEP Datasheet(PDF) 8 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
ADS1278MPAPTEP Datasheet(HTML) 8 Page - Texas Instruments |
|
|
8 / 45 page  CLK t CPW t CLK t CPW t SD t SCLK t DIST t DOHD t SPW Bit23(MSB) Bit22 Bit21 t SPW t DOPD t CD t DS t MSBPD t DIHD · · · t CONV DRDY SCLK DOUT DIN ADS1278-EP SBAS579 – AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V, VREFN = 0 V, and all channels active, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-Speed mode 530 785 mW High-Resolution mode 515 765 mW Power dissipation Low-Power mode 245 355 mW Low-Speed mode 50 80 mW TIMING CHARACTERISTICS: SPI FORMAT TIMING REQUIREMENTS: SPI FORMAT For TA = –40°C to 125°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V. SYMBOL PARAMETER MIN TYP MAX UNIT tCLK CLK period (1/fCLK) (1) 37 10,000 ns tCPW CLK positive or negative pulse width 15 ns tCONV Conversion period (1/fDATA) (2) 256 2560 tCLK tCD (3) Falling edge of CLK to falling edge of DRDY 22 ns tDS (3) Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 tCLK tMSBPD DRDY falling edge to DOUT MSB valid (propagation delay) 16 ns tSD (3) Falling edge of SCLK to rising edge of DRDY 18 ns tSCLK (4) SCLK period 1 tCLK tSPW SCLK positive or negative pulse width 0.4 tCLK tDOHD (5) (3) (6) SCLK falling edge to new DOUT invalid (hold time) 10 ns tDOPD (5) (3) SCLK falling edge to new DOUT valid (propagation delay) 32 ns tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns tDIHD (6) Old DIN valid to falling edge of SCLK (hold time) 6 ns (1) fCLK = 27MHz maximum. (2) Depends on MODE[1:0] and CLKDIV selection. See Table 7 (fCLK/fDATA). (3) Load on DRDY and DOUT = 20pF. (4) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. (5) Timing parameters are characerized or guranteed by design for specified temperature but not production tested. (6) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: ADS1278-EP |
Similar Part No. - ADS1278MPAPTEP |
|
Similar Description - ADS1278MPAPTEP |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
