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TPS3808G12DRVR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS3808G12DRVR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 32 page 6 5 4 1 2 3 RESET GND MR C T SENSE V DD THERMAL PAD 1 2 3 6 5 4 RESET GND MR C T SENSE V DD TPS3808 SBVS050K – MAY 2004 – REVISED OCTOBER 2015 www.ti.com 6 Pin Configuration and Functions DBV Package DRV Package 6-Pin SOT-23 6-Pin (2.00 mm × 2.00 mm) WSON With Thermal Pad Top View Top View Pin Functions PIN I/O DESCRIPTION NAME SOT-23 WSON Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see Electrical Characteristics). CT 4 3 I Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the RESET Delay Time section for more information. GND 2 5 — Ground Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90- MR 3 4 I k Ω pull-up resistor. RESET is an open-drain output that is driven to a low-impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is RESET 1 6 O set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. This pin is connected to the voltage to be monitored. If the voltage at this terminal drops SENSE 5 2 I below the threshold voltage VIT, then RESET is asserted. Supply voltage. It is good analog design practice to place a 0.1- μF ceramic capacitor close VDD 6 1 I to this pin. Thermal — Pad — Thermal Pad. Connect to ground plane to enhance thermal performance of package. Pad 4 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: TPS3808 |
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