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BQ20Z70 Datasheet(PDF) 6 Page - Texas Instruments |
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BQ20Z70 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 17 page  www.ti.com SMBus TIMING SPECIFICATIONS bq20z70 SLUS686B – NOVEMBER 2005 – REVISED JULY 2007 VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSMB SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 kHz fMAS SMBus master clock frequency Master mode, no clock low slave extend 51.2 tBUF Bus free time between start and stop 4.7 tHD:STA Hold time after (repeated) start 4 μs tSU:STA Repeated start setup time 4.7 tSU:STO Stop setup time 4 Receive mode 0 tHD:DAT Data hold time Transmit mode 300 ns tSU:DAT Data setup time 250 tTIMEOUT Error signal/detect See (1) 25 35 ms tLOW Clock low period 4.7 μs tHIGH Clock high period See (2) 4 50 tLOW:SEXT Cumulative clock low slave extend time See (3) 25 ms tLOW:MEXT Cumulative clock low master extend time See (4) 10 tF Clock/data fall time (VILMAX – 0.15 V) to (VIHMIN + 0.15 V) 300 ns tR Clock/data rise time 0.9 VCC to (VILMAX – 0.15 V) 1000 (1) The bq20z70 times out when any clock low exceeds tTIMEOUT. (2) tHIGH:MAX. is minimum bus idle time. SMBC = 1 for t > 50 μs causes reset of any transaction involving the bq20z70 that is in progress. (3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. SMBus TIMING DIAGRAM 6 Submit Documentation Feedback Not Recommended For New Designs |
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