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BQ2201SN-N Datasheet(PDF) 2 Page - Texas Instruments |
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BQ2201SN-N Datasheet(HTML) 2 Page - Texas Instruments |
2 / 15 page As the supply continues to fall past VPFD, an internal switching device forces VOUT to one of the two external backup energy sources. CECON is held high by the VOUT energy source. During power-up, VOUT is switched back to the VCC sup- ply as VCC rises above the backup cell input voltage sourcing VOUT. The CECON output is held inactive for time tCER (120 ms maximum) after the supply has reached VPFD, independent of the CE input, to allow for processor stabilization. During power-valid operation, the CE input is fed through to the CECON output with a propagation delay of less than 10ns. Nonvolatility is achieved by hardware hookup, as shown in Figure 1. Energy Cell Inputs—BC1,BC2 Two primary backup energy source inputs are provided on the bq2201. The BC1 and BC2 inputs accept a 3V pri- mary battery, typically some type of lithium chemistry. If no primary cell is to be used on either BC1 or BC2, the unused input should be tied to VSS. If both inputs are used, during power failure the VOUT output is fed only by BC1 as long as it is greater than 2.5V. If the voltage at BC1 falls below 2.5V, an internal isolation switch automatically switches VOUT from BC1 to BC2. To prevent battery drain when there is no valid data to retain, VOUT and CECON are internally isolated from BC1 and BC2 by either of the following: s Initial connection of a battery to BC1 or BC2,or s Presentation of an isolation signal on CE. A valid isolation signal requires CE low as VCC crosses both VPFD and VSO during a power-down. See Figure 2. Between these two points in time, CE must be brought to the point of (0.48 to 0.52)*VCC and held for at least 700ns. The isolation signal is invalid if CE exceeds 0.54*VCC at any point between VCC crossing VPFD and VSO. The appropriate battery is connected to VOUT and CECON immediately on subsequent application and removal of VCC. 2 FG220101.eps VCC CE BC1 THS VSS VOUT CECON BC2 bq2201 VCC CE CMOS SRAM 5V From Address Decoder 3V Primary Cell 3V Primary Cell Figure 1. Hardware Hookup (5% Supply Operation) Oct. 1998 D TD220101.eps VCC CE VPFD VSO 0.5 VCC 700ns Figure 2. Battery Isolation Signal bq2201 |
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