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ADS7890IPFBT Datasheet(PDF) 5 Page - Texas Instruments |
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ADS7890IPFBT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 29 page ADS7890 SLAS409 − DECEMBER 2003 www.ti.com 5 TIMING REQUIREMENTS All specifications typical at −40 °C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, and 3) PARAMETER SYMBOL MIN TYP MAX UNITS REF FIG. Conversion time t(conv) 365 ns 1,2 Acquisition time t(acq) 187.5 ns 1,2 Cycle time, SCLK t(cyc) 25 ns 1,2 Pulse duration, SCLK low twL 10 ns Pulse duration, SCLK high twH 10 ns DSP INTERFACE Setup time CS low to FS high tsu1 8 ns 2 Delay time FS high to MSB valid td1 9 ns 2 FS pulse duration tw1 15 ns 2 Hold time, SCLK falling edge to FS falling edge (last SCLK falling edge when FS high) th1 5 ns 2 Setup time, FS falling edge to first falling edge of SCLK after FS low tsu2 5 ns 2 Hold time, internal conversion (indicated by tconv) end to FS rising edge to avoid conversion abort th3 10 ns 2 Delay time, 9th SCLK rising edge to FS rising edge for frame abort during sample td8 5 ns 10 SPI INTERFACE Pulse duration, CS minimum tw5 15 ns 1 Hold time, SCLK falling edge (last SCLK falling edge when CS is high) to CS falling edge th2 5 ns 1 Setup time, CS low to first SCLK falling edge after CS low tsu3 5 ns 1 Delay time, CS low to MSB valid td3 9 ns 1 Hold time, internal conversion (indicted by tconv) end to CS falling edge to avoid conversion abort th3 10 ns 1 DSP AND SPI INTERFACE Delay time, SCLK rising edge to SDO valid td2 9 ns 1, 2 Hold time, 16th SCLK falling edge to CS rising edge th4 10 ns 1, 2 Delay time, 16th SCLK falling edge to BUSY rising edge td4 40 ns 1, 2 Pulse duration, BUSY high tw2 365 ns 1, 2 Delay time, 9th SCLK rising edge to CS rising edge for frame abort during sample td8 5 ns 6, 11 Delay time, CS high to SDO three-state td5 10 ns 1, 2 POWER DOWN/RESET Pulse width, low for PWD/RST to reset the device tw3 45 6140 ns 4 Pulse width, low for PWD/RST to power down the device tw4 7200 ns 3 Delay time, power up after PWD/RST is high td6 25 ms 3 Delay time, falling edge of PWD/RST to SDO three-state td7 10 ns 3, 4 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram. (3) All timings are measured with 20-pF equivalent loads at 5 V +VBD and 10-pF equivalent loads at 3 V +VBD on the SDO and BUSY pins. |
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