ADS7891

SLAS410 − DECEMBER 2003

www.ti.com

4

SPECIFICATIONS Continued

TA = −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 3 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL REFERENCE OUTPUT

Start-up time

From 95% (+VA), with 1-

µF storage

capacitor on REFOUT to AGND

120

msec

VREF Range

IOUT=0

2.48

2.5

2.52

V

Source current

Static load

10

µA

Line regulation

+VA = 4.75 V to 5.25 V

1

mV

Drift

IOUT = 0

25

PPM/C

DIGITAL INPUT/OUTPUT

Logic family

CMOS

VIH

IIH = 5 µA

+VBD −1

+VBD + 0.3

V

Logic level

VIL

IIL = 5 µA

−0.3

0.8

V

Logic level

VOH

IOH = 2 TTL loads

+VBD − 0.6

+VBD

V

VOL

IOL = 2 TTL loads

0

0.4

V

Data format

Straight

Binary

POWER SUPPLY REQUIREMENTS

Power supply voltage

+VBD

2.7

3.3

5.25

V

Power supply voltage

+VA

4.75

5

5.25

V

Supply current, +VA, 3 MHz sample rate

17

18

mA

Power dissipation, 3 MHz sample rate

+VA = 5 V

85

90

mW

NAP MODE

Supply current, +VA

2

3

mA

Power-up time(1)

60

nsec

POWER DOWN

Supply current, +VA

2

2.5

µA

Power down time(2)

From simulation results

10

µsec

Power up time

1-

µF Storage capacitor on REFOUT to

AGND

25

msec

Invalid conversions after power up or reset

4

Numbers

TEMPERATURE RANGE

Operating free-air

−40

85

°C

(1) Minimum acquisition time for first sampling after the end of nap state must be 60 nsec more than normal.

(2) Time required to reach level of 2.5 µA.