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ADS7861IBRHBTG4 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS7861IBRHBTG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 32 page ADS7861 11 SBAS110D FIGURE 8. Conversion Mode. HIGH within this window, it is then uncertain as to when the ADS7861 will initiate conversion (see Figure 8 for a more detailed description). Sixteen clock cycles are required to perform a single conversion. Immediately following CONVST switching to HIGH, the ADS7861 will switch from the sample mode to the hold mode asynchronous to the external clock. The BUSY output pin will then go HIGH and remain HIGH for the duration of the conversion cycle. On the falling edge of the first cycle of the external clock, the ADS7861 will latch in the address for the next conversion cycle depending on the status of the A0 pin (HIGH = Channel 1, LOW = Channel 0). The address must be selected 15ns prior to the falling edge of cycle one of the external clock and must remain ‘held’ for 15ns following the clock edge. For maximum throughput time, the CONVST and RD pins should be tied together. CS must be brought LOW to enable the two serial outputs. Data will be valid on the falling edge of all 16 clock cycles per conversion. The first bit of data will be a status flag for either Channel 0 or 1, the second bit will be a second status flag for either Channel A or B. The subsequent data will be MSB-first through the LSB, followed by two zeros (see Table II and Figures 9 and 10). SYMBOL DESCRIPTION MIN TYP MAX UNITS COMMENTS tCONV Conversion Time 1.75 µs When TCKP = 125ns tACQ Acquisition Time 0.25 µs When TCKP = 125ns tCKP Clock Period 125 5000 ns tCKL Clock LOW 40 ns tCKH Clock HIGH 40 ns tF DOUT Fall Time 25 ns tR DOUT Rise Time 30 ns t1 CONVST HIGH 15 ns t2 Address Setup Time 15 ns Address latched on falling edge of CLK cycle ‘2’ t3 Address Hold Time 15 t4 RD Setup Time 15 ns Before falling edge of CLOCK t5 RD to CS Hold Time 15 ns After falling edge of CLOCK t6 CONVST LOW 20 ns t7 RD LOW 20 ns t8 CS to Data Valid 25 ns t9 CLOCK to Data Valid Delay 30 ns Maximum delay following rising edge of CLOCK t10 Data Valid After CLOCK(1) 1 ns Time data is valid after second rising edge of CLOCK NOTE: (1) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle. TIMING SPECIFICATIONS CLOCK CYCLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SERIAL DATA CH0 OR CH1 CHA OR CHB DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 TABLE II. Serial Data Output Format. NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock (Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge. CLOCK CONVST Cycle 1 Cycle 2 t CKP 125ns 10ns 5ns 10ns 5ns A B C |
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