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ADS8910B Datasheet(PDF) 9 Page - Texas Instruments |
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ADS8910B Datasheet(HTML) 9 Page - Texas Instruments |
9 / 68 page 9 ADS8910B ADS8912B ADS8914B www.ti.com SBAS707A – JUNE 2016 – REVISED JULY 2016 Product Folder Links: ADS8910B ADS8912B ADS8914B Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 6.7 Switching Characteristics At RVDD = 5.5 V, DVDD = 2.35 V to 3.6 V, VREF = 5 V, and maximum throughput (unless otherwise noted). Minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C. PARAMETER MIN TYP MAX UNIT TIMING DIAGRAM CONVERSION CYCLE tconv Conversion time ADS8910B 580 640 ns Figure 1 ADS8912B 1100 1200 ADS8914B 2400 2500 ASYNCHRONOUS RESET, AND LOW POWER MODES td_rst Delay time: RST rising to RVS rising 3 ms Figure 2 tPU_ADC Power-up time for converter module 1 ms See PD_CNTL Register tPU_REFBUF Power-up time for internal reference buffer, CREFBUF = 22 µF 10 ms tPU_Device Power-up time for device CLDO = 1 µF, CREFBUF = 22 µF 10 ms SPI-COMPATIBLE SERIAL INTERFACE tden_CSDO Delay time: CS falling to data enable 9 ns Figure 3 tdz_CSDO Delay time: CS rising to SDO going to Hi-Z 10 ns td_CKDO Delay time: SCLK launch edge to (next) data valid on SDO 13 ns td_CSRDY_f Delay time: CS falling to RVS falling 12 ns Figure 4 td_CSRDY_r Delay time: CS rising to RVS rising After NOP operation 30 ns Figure 4 After WR or RD operation 120 SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock) td_CKSTR_r Delay time: SCLK launch edge to RVS rising 13 ns Figure 4 td_CKSTR_f Delay time: SCLK launch edge to RVS falling 13 ns toff_STRDO_f Time offset: RVS falling to (next) data valid on SDO -2 2 ns toff_STRDO_r Time offset: RVS rising to (next) data valid on SDO -2 2 ns SOURCE-SYNCHRONOUS SERIAL INTERFACE (Internal Clock) td_CSSTR Delay time: CS falling to RVS rising 15 50 ns Figure 5 tSTR Strobe output time period INTCLK option 15 ns INTCLK / 2 option 30 INTCLK / 4 option 60 tph_STR Strobe output high time 0.45 0.55 tSTR tpl_STR Strobe output low time 0.45 0.55 tSTR |
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