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AMC1305M05 Datasheet(PDF) 6 Page - Texas Instruments |
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AMC1305M05 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 39 page  6 10 ) ( u ¸¸ ¹ · ¨¨ © § u TempRange value value value ppm TCE MIN MAX G TempRange value value TCE MIN MAX O (2) Offset error drift is calculated using the box method as described by the following equation: (3) Gain error drift is calculated using the box method as described by the following equation: AMC1305L25, AMC1305M05, AMC1305M25 SBAS654C – JUNE 2014 – REVISED DECEMBER 2014 www.ti.com 8.10 Electrical Characteristics: AMC1305M05 All minimum and maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc 3 filter with OSR = 256, unless otherwise noted. Typical values are at T A = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Maximum differential voltage input range VClipping ±62.5 mV (AINP-AINN) Specified linear full-scale range FSR –50 50 mV (AINP-AINN) VCM Operating common-mode input range –0.032 AVDD – 2 V CID Differential input capacitance 2 pF IIB Input current Inputs shorted to AGND –97 -72 -57 μA RID Differential input resistance 5 k Ω IOS Input offset current ±5 nA CMTI Common-mode transient immunity 15 kV/ μs fIN = 0 Hz, 104 dB VCM min ≤ VIN ≤ VCM max CMRR Common-mode rejection ratio fIN from 0.1 Hz to 50 kHz, 75 dB VCM min ≤ VIN ≤ VCM max BW Input bandwidth 800 kHz DC ACCURACY DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB INL Integral nonlinearity(1) Resolution: 16 bits –4 ±1.5 4 LSB EO Offset error Initial, at 25°C –50 ±2.5 50 µV TCEO Offset error thermal drift(2) –1.3 1.3 μV/°C EG Gain error Initial, at 25°C –0.3 -0.02 0.3 % TCEG Gain error thermal drift(3) –40 ±20 40 ppm/°C PSRR Power-supply rejection ratio VAVDD from 4.5 to 5.5V, at dc 105 dB AC ACCURACY SNR Signal-to-noise ratio fIN = 1 kHz 76 81 dB SINAD Signal-to-noise + distortion fIN = 1 kHz 76 81 dB THD Total harmonic distortion fIN = 1 kHz -90 –83 dB SFDR Spurious-free dynamic range fIN = 1 kHz 83 92 dB DIGITAL INPUTS/OUTPUTS External Clock fCLKIN Input clock frequency 5 20 20.1 MHz DutyCLKIN Duty cycle 5 MHz ≤ fCLKIN ≤ 20.1 MHz 40 50 60 % CMOS Logic Family, CMOS with Schmitt-Trigger IIN Input current DGND ≤ VIN ≤ DVDD –1 1 μA CIN Input capacitance 5 pF VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V VIL Low-level input voltage –0.3 0.3 × DVDD V CLOAD Output load capacitance fCLKIN = 20 MHz 30 pF IOH = –20 µA DVDD – 0.1 V VOH High-level output voltage IOH = –4 mA DVDD – 0.4 V IOL = 20 µA 0.1 V VOL Low-level output voltage IOL = 4 mA 0.4 V (1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR. 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AMC1305L25 AMC1305M05 AMC1305M25 |
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