bq26501

SLUS586B − OCTOBER 2003 − REVISED MARCH 2004

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APPLICATION INFORMATION

REGISTER DESCRIPTIONS

Device Control Register (CTRL) − Address 0x00

The device control register is used by the host system to request special operations by the bq26501. The highest

priority command set in the MODE register performs when the host writes data 0xA9 to the control register. The

CTRL register is cleared when the action is complete. Note that writing any value other than 0xA9 has no effect.

Mode Register (MODE) − Address 0x01

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

NAME

GPIEN

GPSTAT

WRTNAC

DONE

PRST

POR

FRST

SHIP

MODE

REGISTER

DESCRIPTION

GPIEN

GPIEN sets the state of the GPIO pin. A “1” configures the GPIO pin as input, while a “0” configures the GPIO pin

as an open-drain output. This bit is initialized to the value of bit 7 of the PKCFG register in the EEPROM

GPSTAT

GPSTAT sets the state of the open drain output of the GPIO pin (GPIEN = 0). A “1” turns off the open drain out-

put while a “0” turns the output on. This bit is set to 1 on POR. When the GPIO pin is an input (GPIEN=1), this bit

returns the logic state of the GPIO pin.

WRTNAC

WRTNAC is used to transfer data from the AR registers to the NAC registers. Other registers are updated as

appropriate. This command is useful during the pack manufacture and test to initialize the gauge to match the

estimated battery capacity. This bit is cleared on all resets.

DONE

DONE is used to write NAC to LMD. Useful if the host uses a charge termination method that does not allow the

monitor to detect the taper current. The host system could use this command when the charging is complete to

force update of internal registers to a full battery condition. This bit is cleared on all resets.

PRST

Partial reset. This command requests a full reset, except that the NAC, LMD, and the CI bit in FLAGS should not

be restored to their initial values. This command is intended for manufacturing use. This bit is cleared on all re-

sets.

POR

The POR status bit is set to “1” by the bq26501 following a power-on-reset (POR). This is a flag to the host that

VCC was less than V(POR) and caused a reset. The bit is cleared to “0” by the bq26501 when a full charge condi-

tion is reached or it may be cleared by the host. The host may set this bit, but it has no effect on the bq26501

operation.

FRST

Full reset. This command bit requests a full reset. A full reset re-initializes all RAM registers, including the NAC,

LMD, and FLAGS registers. This command is intended for manufacturing use. This bit is cleared on all resets.

SHIP

This command bit requests that the device should be put in ship mode. See the Power Modes section for a de-

scription of the ship mode. This command is intended for manufacturing use. This bit is cleared on all resets.

WRTNAC, DONE, PRST, FRST, and SHIP commands are prioritized in bit order. This means that WRTNAC

(bit 5) has higher priority than DONE (bit 4); PRST (bit 3) has higher priority than FRST (bit 1), and so on. Only

the highest priority mode set is enabled each time the CTRL register is written with data 0xA9, and the firmware

clears all other mode bits and the CTRL register when that action is complete. The host system must make two

writes for every mode to be enabled, one write to the mode register to set the appropriate bit and a second write

to the CTRL register to signal that the mode should be enabled.

Not Recommended For New Designs