1

2

3

4

13

14

15

SCLK

DAC108S085

SYNC

16

5

6

7

8

9

10

11

12

GND

1

2

3

4

DAC108S085

9

10

11

12

DAC108S085

www.ti.com

SNAS423B – AUGUST 2007 – REVISED MARCH 2013

Pin Configuration

PIN DESCRIPTIONS

WQFN

TSSOP

Symbol

Type

Description

Pin No.

Pin No.

1

3

Analog Output

Channel A Analog Output Voltage.

2

4

Analog Output

Channel B Analog Output Voltage.

3

5

Analog Output

Channel C Analog Output Voltage.

4

6

Analog Output

Channel D Analog Output Voltage.

5

7

Supply

Power supply input. Must be decoupled to GND.

Unbuffered reference voltage shared by Channels A, B, C, and D.

6

8

Analog Input

Must be decoupled to GND.

Unbuffered reference voltage shared by Channels E, F, G, and H.

7

9

Analog Input

Must be decoupled to GND.

8

10

GND

Ground

Ground reference for all on-chip circuitry.

9

11

Analog Output

Channel H Analog Output Voltage.

10

12

Analog Output

Channel G Analog Output Voltage.

11

13

Analog Output

Channel F Analog Output Voltage.

12

14

Analog Output

Channel E Analog Output Voltage.

Frame Synchronization Input. When this pin goes low, data is written

into the DAC's input shift register on the falling edges of SCLK. After

the 16th falling edge of SCLK, a rising edge of SYNC causes the

13

15

SYNC

Digital Input

DAC to be updated. If SYNC is brought high before the 15th falling

edge of SCLK, the rising edge of SYNC acts as an interrupt and the

write sequence is ignored by the DAC.

Serial Clock Input. Data is clocked into the input shift register on the

14

16

SCLK

Digital Input

falling edges of this pin.

Serial Data Input. Data is clocked into the 16-bit shift register on the

15

1

Digital Input

falling edges of SCLK after the fall of SYNC.

16

2

Digital Output

cycles.

Exposed die attach pad can be connected to ground or left floating.

PAD

17

Ground

Soldering the pad to the PCB offers optimal thermal performance

(WQFN only)

and enhances package self-alignment during reflow.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2007–2013, Texas Instruments Incorporated

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