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74LVCH16374ADLRG4 Datasheet(PDF) 11 Page - Texas Instruments |
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74LVCH16374ADLRG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 24 page 1OE 1CLK 1D1 To Seven Other Channels 1Q1 2OE 2CLK 2D1 2Q1 To Seven Other Channels C1 1D C1 1D SN74LVCH16374A www.ti.com SCAS757B – DECEMBER 2003 – REVISED SEPTEMBER 2014 9 Detailed Description 9.1 Overview This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. Active bus-hold circuitry holds unused or not driven inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. The SN74LVCH16374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 9.2 Functional Block Diagram Figure 4. Logic Diagram (Positive Logic) Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SN74LVCH16374A |
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