Electronic Components Datasheet Search |
|
74LVCH16901DGGRE4 Datasheet(PDF) 1 Page - Texas Instruments |
|
74LVCH16901DGGRE4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page www.ti.com FEATURES DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1CLKENAB LEAB CLKAB 1ERRA 1APAR GND 1A1 1A2 1A3 VCC 1A4 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 2A5 VCC 2A6 2A7 2A8 GND 2APAR 2ERRA OEAB SEL 2CLKENAB 1CLKENBA LEBA CLKBA 1ERRB 1BPAR GND 1B1 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 2B5 VCC 2B6 2B7 2B8 GND 2BPAR 2ERRB OEBA ODD/EVEN 2CLKENBA DESCRIPTION/ORDERING INFORMATION SN74LVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES145C – OCTOBER 1998 – REVISED JUNE 2005 • Member of the Texas Instruments Widebus+™ Family • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes • Operates From 1.65 V to 3.6 V • Inputs Accept Voltages to 5.5 V • Max tpd of 5.4 ns at 3.3 V • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C • Simultaneously Generates and Checks Parity • Option to Select Generate Parity and Check or Feedthrough Data/Parity in A-to-B or B-to-A Direction • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) • Ioff Supports Partial-Power-Down Mode Operation • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class I • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver, or it can generate/check parity from the two 8-bit data buses in either direction. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C TSSOP – DGG Tape and reel SN74LVCH16901DGGR LVCH16901 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+, UBT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1998–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Not Recommended For New Designs |
Similar Part No. - 74LVCH16901DGGRE4 |
|
Similar Description - 74LVCH16901DGGRE4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |