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DAC5686 Datasheet(PDF) 11 Page - Texas Instruments |
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DAC5686 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 53 page  TYPICAL CHARACTERISTICS 0 2 4 6 8 10 G001 0 10000 20000 30000 40000 50000 60000 70000 Input Code –2 –4 –6 –8 –10 DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Data output delay after falling td(DATA) 10 ns edge of SCLK Parallel Data Input Timing, CLK1 Latching (PLL Mode and Dual Clock Mode) Setup time, data valid to rising tsu(DATA) 0.3 –0.4 ns edge of CLK1 Hold time, data valid after rising th(DATA) 1.2 0.6 ns edge of CLK1 Timing Parallel Data Input (External Clock Mode, CLK2 Input) High-impedance load on PLLLOCK. Setup time, DATA valid to rising tsu(DATA) Note that tsu increases with a 4.6 3 ns edge of PLLLOCK lower-impedance load. High-impedance load on PLLLOCK. Hold time, DATA valid after rising Note that th decreases (becomes th(DATA) –0.8 –2.4 ns edge of PLLLOCK more negative) with a lower-impedance load. High-impedance load on PLLLOCK. Delay from CLK2 rising edge to Note that PLLLOCK delay td(PLLLock) 2.5 4.2 6.5 ns PLLLOCK rising edge increases with a lower-impedance load. INTEGRAL NONLINEARITY ERROR vs INPUT CODE Figure 1. Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): DAC5686 |
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