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DAC7615PG4 Datasheet(PDF) 4 Page - Texas Instruments |
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DAC7615PG4 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 17 page  ® 4 DAC7615 PIN CONFIGURATION—P, U Packages Top View PDIP, SOIC PIN CONFIGURATION—E Package Top View SSOP PIN DESCRIPTIONS—E Package PIN LABEL DESCRIPTION 1VDD Positive Analog Supply Voltage, +5V nominal. 2VOUTD DAC D Voltage Output 3VOUTC DAC C Voltage Output 4VREFL Reference Input Voltage Low. Sets minimum out- put voltage for all DACs. 5 NIC Not Internally Connected. 6 NIC Not Internally Connected. 7VREFH Reference Input Voltage High. Sets maximum out- put voltage for all DACs. 8VOUTB DAC B Voltage Output 9VOUTA DAC A Voltage Output 10 VSS Negative Analog Supply Voltage, 0V or –5V nomi- nal. 11 GND Ground 12 SDI Serial Data Input 13 CLK Serial Data Clock 14 CS Chip Select Input 15 NIC Not Internally Connected. 16 NIC Not Internally Connected. 17 LOADDACS All DAC registers becomes transparent when LOADDACS is LOW. They are in the latched state when LOADDACS is HIGH. 18 LOADREG The selected input register becomes transparent when LOADREG is LOW. It is in the latched state when LOADREG is HIGH. 19 RESET Asynchronous Reset Input. Sets all DAC registers to either zero-scale (000H) or mid-scale (800H) when LOW. RESETSEL determines which code is active. 20 RESETSEL When LOW, a LOW on RESET will cause all DAC registers to be set to code 000H. When RESETSEL is HIGH, a LOW on RESET will set the registers to code 800H. PIN DESCRIPTIONS—P, U Packages PIN LABEL DESCRIPTION 1VDD Positive Analog Supply Voltage, +5V nominal. 2VOUTD DAC D Voltage Output 3VOUTC DAC C Voltage Output 4VREFL Reference Input Voltage Low. Sets minimum out- put voltage for all DACs. 5VREFH Reference Input Voltage High. Sets maximum out- put voltage for all DACs. 6VOUTB DAC B Voltage Output 7VOUTA DAC A Voltage Output 8VSS Negative Analog Supply Voltage, 0V or –5V nomi- nal. 9 GND Ground 10 SDI Serial Data Input 11 CLK Serial Data Clock 12 CS Chip Select Input 13 LOADDACS All DAC registers become transparent when LOADDACS is LOW. They are in the latched state when LOADDACS is HIGH. 14 LOADREG The selected input register becomes transparent when LOADREG is LOW. It is in the latched state when LOADREG is HIGH. 15 RESET Asynchronous Reset Input. Sets DAC and input registers to either zero-scale (000H) or mid-scale (800H) when LOW. RESETSEL determines which code is active. 16 RESETSEL When LOW, a LOW on RESET will cause the DAC and input registers to be set to code 000H. When RESETSEL is HIGH, a LOW on RESET will set the registers to code 800H. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V DD V OUTD V OUTC V REFL V REFH V OUTB V OUTA V SS RESETSEL RESET LOADREG LOADDACS CS CLK SDI GND DAC7615P, U 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 V DD V OUTD V OUTC V REFL NIC NIC V REFH V OUTB V OUTA V SS RESETSEL RESET LOADREG LOADDACS NIC NIC CS CLK SDI GND DAC7615E |
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Similar Description - DAC7615PG4 |
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