CDC2510B

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

AVCC, VCC

MIN

TYP‡

MAX

UNIT

VIK

II = −18 mA

3 V

−1.2

V

IOH = −100 µA

MIN to MAX

VCC −0.2

VOH

IOH = −12 mA

3 V

2.1

V

VOH

IOH = − 6 mA

3 V

2.4

V

IOL = 100 µA

MIN to MAX

0.2

VOL

IOL = 12 mA

3 V

0.8

V

VOL

IOL = 6 mA

3 V

0.55

V

II

VI = VCC or GND

3.6 V

±5

µA

ICC§

VI = VCC or GND,

IO = 0, Outputs: low or high

3.6 V

10

µA

∆ICC

One input at VCC − 0.6 V,

Other inputs at VCC or GND

3.3 V to 3.6 V

500

µA

Ci

VI = VCC or GND

3.3 V

4

pF

Co

VO = VCC or GND

3.3 V

6

pF

‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

§ For ICC of AVCC and ICC vs Frequency (see Figures 7 and 8).

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

fclk

Clock frequency

25

125

MHz

Input clock duty cycle

40%

60%

Stabilization time†

1

ms

† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,

and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under

SSC application.

switching characteristics over recommended ranges of supply voltage and operating free-air

PARAMETER

FROM

(INPUT)/CONDITION

TO

(OUTPUT)

VCC, AVCC = 3.3 V

± 0.165 V

VCC, AVCC = 3.3 V

± 0.3 V

UNIT

PARAMETER

(INPUT)/CONDITION

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

tphase error, − jitter

(see Notes 7 and 8,

Figures 3, 4, and 5)

CLKIN

↑ = 66 MHz to 100 MHz

FBIN

↑

−150

150

−200

200

ps

tsk(o)§

Any Y or FBOUT

Any Y or FBOUT

200

ps

Jitter(pk-pk) (see Figure 6)

Any Y or FBOUT

−80

80

Jitter(cycle-cycle)

(See Figure 6)

Clkin = 66 MHz to 100 MHz

Any Y or FBOUT

|100|

ps

Duty cycle reference

(see Figure 4)

F(clkin > 60 MHz)

Any Y or FBOUT

45%

55%

tr

Any Y or FBOUT

1.3

1.9

0.8

2.1

ns

tf

Any Y or FBOUT

1.7

2.5

1.2

2.7

ns

‡ These parameters are not production tested.

§ The tsk(o) specification is only valid for equal loading of all outputs.

NOTES:

6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

7. This is considered as static phase error.

8. Phase error does not include jitter. The total phase error is − 230 ps to 230 ps for the 5% VCC range.