Electronic Components Datasheet Search |
|
CDC2516DGGR Datasheet(PDF) 1 Page - Texas Instruments |
|
|
CDC2516DGGR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 15 page CDC2516 3.3V PHASELOCK LOOP CLOCK DRIVER SCAS579C − OCTOBER 1996 − REVISED DECEMBER 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Use CDCVF2510A as a Replacement for this Device D Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications D Distributes One Clock Input to Four Banks of Four Outputs D Separate Output Enable for Each Output Bank D External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input D On-Chip Series-Damping Resistors D No External RC Network Required D Operates at 3.3-V VCC D Packaged in Plastic 48-Pin Thin Shrink Small-Outline Package description The CDC2516 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground. The CDC2516 is characterized for operation from 0 °C to 70°C. Copyright 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VCC 1Y0 1Y1 GND GND 1Y2 1Y3 VCC 1G GND AVCC CLK AGND AGND GND 2G VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC VCC 4Y0 4Y1 GND GND 4Y2 4Y3 VCC 4G GND AVCC FBIN AGND FBOUT GND 3G VCC 3Y0 3Y1 GND GND 3Y2 3Y3 VCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DGG PACKAGE (TOP VIEW) |
Similar Part No. - CDC2516DGGR |
|
Similar Description - CDC2516DGGR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |