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PLL DIVIDER SELECTION

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

CDCFR83A

SCAS812 – AUGUST 2005

Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted,

provided that (267 MHz < BUSCLK < 533 MHz) and (33 MHz < REFCLK < 100 MHz).

Table 1. REFCLK and BUSCLK Frequencies

MULT0

MULT1

REFCLK

MULTIPLY

(MHz)

RATIO

(MHz)

0

0

67

4

267

0

1

50

6

300

0

1

67

6

400

1

1

33

8

267

1

1

50

8

400

1

1

67

8

533

1

0

67

16/3

356

(1)

BUSCLK will be undefined until a valid reference clock is available at REFCLK. After applying

REFCLK, the PLL requires stabilization time to achieve phase lock.

Table 2. Clock Output Driver States

STATE

PWRDNB

STOPB

CLK

CLKB

Powerdown

0

X

GND

GND

CLK stop

1

0

Normal

1

1

PACLKB/PLLCLKB/REFCLKB

(1)

Depending on the state of S0, S1, and S2

UNIT

–0.5 V to 4 V

Output voltage range at any output terminal

Input voltage rangeat any input terminal

Continuous total power dissipation

See Dissipation Rating Table

Operating free-air temperature range

–40

°C to 85°C

Storage temperature range

–65

°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to the GND terminals.

PACKAGE

DERATING FACTOR

POWER RATING

POWER RATING

POWER RATING

DBQ

1400 mW

11 mW/

°C

905 mW

740 mW

(1)

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

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