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AD5641AKS Datasheet(PDF) 3 Page - Analog Devices |
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AD5641AKS Datasheet(HTML) 3 Page - Analog Devices |
3 / 20 page Preliminary Technical Data AD5641 Rev. PrC | Page 3 of 20 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. B Version1 Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 14 Bits Relative Accuracy2 ±4 LSB B Grade ±8 LSB A Grade Differential Nonlinearity2 ±1 LSB Guaranteed monotonic by design Zero Code Error ±0.2 mV All 0s loaded to DAC register Offset Error ±0.125 % of FSR Full-Scale Error ±0.01 LSB All 1s loaded to DAC register Gain Error ±0.04 % of FSR Zero Code Error Drift 5.0 µV/°C Gain Temperature Coefficient 2.0 ppm of FSR/°C OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VDD V Output Voltage Settling Time 8 18 µs Code ¼ to ¾ Slew Rate 0.5 V/µs Capacitive Load Stability 470 pF RL = ∞ 1000 pF RL = 2 kΩ Output Noise Spectral Density 120 nV/Hz DAC code = TBD, 10 kHz Noise TBD DAC code = TBD, 0.1 Hz to 10 Hz bandwidth Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Digital Feedthrough 0.5 nV-s DC Output Impedance 1 Short-Circuit Current 20 mA VDD = 3 V/5 V LOGIC INPUTS Input Current ±1 µA VINL, Input Low Voltage 0.8 V VDD = 5 V 0.6 V VDD = 2.7 V VINH, Input High Voltage 1.8 V VDD = 5 V 1.4 V VDD = 2.7 V Pin Capacitance 3 pF POWER REQUIREMENTS VDD 2.7 5.5 V All digital inputs at 0 or VDD IDD (Normal Mode) DAC active and excluding load current VDD = 4.5 V to 5.5 V 100 µA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 70 µA VIH = VDD and VIL = GND IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.2 1 µA VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 0.05 1 µA VIH = VDD and VIL = GND POWER EFFICIENCY IOUT/IDD TBD % ILOAD = 2 mA and VDD = ±5 V 1 Temperature ranges are as follows: B Version: –40°C to +125°C, typical at +25°C. 2 Linearity calculated using a reduced code range. 3 Guaranteed by design and characterization, not production tested. |
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