CDCR81

DIRECT RAMBUS

™ CLOCK GENERATOR

SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999

7

POST OFFICE BOX 655303

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tc(out)

Clock output cycle time

2.5

3.75

ns

t

Total cycle jitter over 1, 2,

Stopped phase

alignment

267 MHz –

400 MHz

See Figure 3

60

ps

t(jitter)

Total cycle jitter over 1, 2,

3, 4, 5, or 6 clock cycles

Infinite phase

267 MHz

See Figure 3

80

ps

alignment

300 MHz

See Figure 3

70

ps

t(phase)

Phase detector phase error for distributed loop

Static phase error

–50

50

ps

t(phase, SSC)

PLL output phase error when tracking SSC

Dynamic phase error

–100

100

ps

t(DC)

Output duty cycle over 10,000 cycles

See Figure 4

45%

55%

Stopped phase

alignment

267 MHz –

400 MHz

See Figure 5

50

ps

t(DC, err)

Output cycle-to-cycle

duty cycle error

Ifiit

h

267 MHz

70

(DC, err)

duty cycle error

Infinite phase

alignment

300 MHz

See Figure 5

80

ps

alignment

400 MHz

90

tr, tf

Output rise and fall times (measured at 20%-80% of

output voltage)

See Figure 7

200

450

ps

∆t

Difference between rise and fall times on a single device

(20%–80%) |tf – tr|

See Figure 7

100

ps

† All typical values are at VDD = 3.3 V, TA = 25°C.

state transition latency specifications

PARAMETER

FROM

TO

TEST

CONDITIONS

MIN

TYP†

MAX

UNIT

t()

Delay time, PWRDNB

↑ to CLK/CLKB output

settled (excluding t(DISTLOCK))

Power-

Normal

See Figure 8

3

ms

t(powerup)

Delay time, PWRDNB

↑ to internal PLL and

clock are on and settled

down

Normal

3

ms

)

Delay time, powerup to CLK/CLKB output

settled

VDD

Normal

See Figure 8

3

ms

Delay time, powerup to internal PLL and clock

are on and settled

VDD

Normal

3

ms

t(MULT)

MULT0 and MULT1 change to CLK/CLKB

output resettled (excluding t(DISTLOCK))

Normal

Normal

See Figure 9

1

ms

t(CLKON)

STOPB

↑ to CLK/CLKB glitch-free clock edges

CLK

Stop

Normal

See Figure 10

10

ns

t(CLKSETL)

STOPB

↑ to CLK/CLKB output settled to within

50 ps of the phase before STOPB was disabled

CLK

Stop

Normal

See Figure 10

20

cycles

t(CLKOFF)

STOPB

↑ to CLK/CLKB output disabled

Normal

CLK

Stop

See Figure 10

5

ns

t(powerdown)

Delay time, PWRDNB

↓ to the device in power-

down mode

STOPB

Power-

down

1

ms

t(STOP)

Maximum time in CLKSTOP (STOPB = 0)

before re-entering normal mode (STOPB = 1)

STOPB

Normal

100

µs